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74LV4094 8-stage shift-and-store bus register
Product specification 1998 Jun 23
Philips Semiconductors
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
FEATURES
* Optimized for low voltage applications: 1.0 to 3.6 V * Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V * Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, * Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, * Output capability: standard * ICC category: MSI
Applications: Tamb = 25C Tamb = 25C
DESCRIPTION
The 74LV4094 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT4094. The 74LV4094 is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input (D) to the parallel buffered 3-State outputs (QP0 to OP7). The parallel outputs may be connected directly to the common bus lines. Data is shifted on the positive-going clock (CP) transitions. The data in each shift register is transferred to the storage register when the strobe input (STR) is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of 74LV4094 devices. Data is available at QS1 on the positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at QS2 on the next negative going clock edge and is for cascading 74LV4094 devices when the clock rise time is slow.
* Serial-to-parallel data conversion * Remote control holding register
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr =tf 2.5 ns SYMBOL PARAMETER Propagation delay CP to QS1 CP to QS2 CP to QPn STR to QPn Maximum clock frequency Input capacitance Power dissipation capacitance per gate
CONDITIONS CL = 15 pF; VCC = 3.3 V
TYPICAL 14 13 18 17 95 3.5
UNIT
tPHL/tPLH
ns
fMAX CI CPD
MHz pF pF
VCC = 3.3 V VI = GND to VCCNO TAG
83
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi ) (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO TEMPERATURE RANGE -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV4094 N 74LV4094 D NORTH AMERICA 74LV4094 N 74LV4094 D PKG. DWG. # SOT38-4 SOT109-1
PIN CONFIGURATION
STR D CP QP0 QP1 QP2 QP3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OE QP4 QP5 QP6 QP7 QS2 QS1
PIN DESCRIPTION
PIN NUMBER 1 2 3 4, 5, 6, 7, 14, 13, 12, 11 8 9, 10 15 16 SYMBOL STR D CP QP0 to QP7 GND QS1, QS2 OE VCC FUNCTION Strobe input Serial input Clock input Parallel outputs Ground (0 V) Serial outputs Output enable input Positive supply voltage
SV01611
1998 Jun 23
2
853-2078 19619
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
LOGIC SYMBOL
3 1
LOGIC SYMBOL (IEEE/IEC)
1 15 CP STR QS1 QS2 QP0 QP1 9 SRG8 10 4 5 6 7 7 QP4 QP5 QP6 QP7 OE 14 14 13 12 12 11 11 9 15 13 2 1D 2D 3 4 5 6 QP3 3 C1/ C2 EN3
2
QP2 D
SV01612
10
FUNCTIONAL DIAGRAM
D CP
SV01613
2 3
8-STATE SHIFT REGISTER
QS2 QS1
10 9
1
STR
8-BIT STORAGE REGISTER
15
OE
3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 Q51 QP6 QP7 4 5 6 7 14 13 12 11
SV01614
LOGIC DIAGRAM
STAGE 0 D D Q FF0 CP CP CP D STAGES 1 TO 6 Q STAGE 7 D Q D CP latch D Q D Q Q Q7' QS2
FF7 CP
latch CP STR OE
latch CP
QP0
QP1 QP2
QP3 QP4
QP5 QP6
QP7
SV01615
1998 Jun 23
3
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
FUNCTION TABLE
INPUTS CP OE L L H H H H STR X X L H H H D X X X L H H PARALLEL OUTPUT QP0 Z Z NC L H NC QPn Z Z NC QPn-1 QPn-1 NC SERIAL OUTPUTS QS1 Q'6 NC Q'6 Q'6 Q'6 NC QS2 NC QP7 NC NC NC QP7
NOTES: H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state NC = no change
= LOW-to-HIGH CP transition = HIGH-to-LOW CP transition Q'6 = the information in the 8th register stage is transferred to the 8th register stage and QSn clock edge.
TIMING DIAGRAM
CLOCK INPUT CP
DATA INPUT
D
STROBE INPUT
STR
OUTPUT ENABLE INPUT
OE
INTERNAL Q'0 (FF0) Z-state
OUTPUT
QP0
INTERNAL Q'6 (FF6) Z-state
OUTPUT
QP6 QS1 QS2
SERIAL OUTPUT
SERIAL OUTPUT
SV01616
1998 Jun 23
4
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
ABSOLUTE MAXIMUM RATINGSNO TAG, NO TAG
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL VCC "IIK "IOK "IO "IGND, "ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs DC VCC or GND current for types with - standard outputs Storage temperature range Power dissipation per package - plastic DIL - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12 mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +7.0 20 50 25 50 -65 to +150 750 500 400 UNIT V mA mA mA mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V PARAMETER DC supply voltage CONDITIONS See Note NO TAG MIN 1.0 0 0 -40 -40 - - - - - - TYP 3.3 - - MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V C ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
1998 Jun 23
5
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, voltages are referenced to GND (ground = 0 V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN HIGH level Input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 to 3.6 V VIL LOW level Input voltage VCC = 1.2 V VCC = 2.0 V VCC = 2.7 to 3.6 V VCC = 1.2 V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; all outputs HIGH level output voltage; STANDARD outputs VCC = 2.0 V; VI = VIH or VIL; -IO = 100A VCC = 2.7 V; VI = VIH or VIL; -IO = 100A VCC = 3.0 V; VI = VIH or VIL; -IO = 100A VOH VCC = 3.0 V; VI = VIH or VIL; -IO = 6mA VCC = 1.2 V; VI = VIH or VIL; IO = 100A VOL LOW level output voltage; all outputs LOW level output voltage; STANDARD outputs Input leakage current 3-State output OFF-state current Quiescent supply current; SSI Quiescent supply current; flip-flops ICC Quiescent supply current; MSI Quiescent supply current; LSI ICC Additional quiescent supply current per input VCC = 2.0 V; VI = VIH or VIL; IO = 100A VCC = 2.7 V; VI = VIH or VIL; IO = 100A VCC = 3.0 V; VI = VIH or VIL; IO = 100A VOL VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V 1.8 2.5 2.8 2.20 V V VCC 1.4 2.0 0.4 GND 0.6 0.8 -40C to +85C TYP
NO TAG
-40C to +125C MAX MIN VCC 1.4 2.0 GND 0.6 0.8 MAX
UNIT
0.6
VIH
V
V
II IOZ ICC
VCC = 3.6 V; VI = VCC or GND VCC = 3.6 V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6; VI = VCC or GND; IO = 0 VCC = 3.6; VI = VCC or GND; IO = 0 VCC = 3.6 V; VI = VCC or GND; IO = 0 VCC = 3.6 V; VI = VCC or GND; IO = 0 VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V
1.0 5 20.0 20.0 20.0 500 500
1.0 10 40 80 160
A A A A
A 1000 850 A
NOTE: 1. All typical values are measured at Tamb = 25C.
1998 Jun 23
6
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
AC CHARACTERISTICS
GND = 0 V; tr = tf 2.5ns; CL = 50pF CONDITION SYMBOL PARAMETER WAVEFORM VCC (V) 1.2 tPHL/tPLH Propagation delay g y CP to QS1 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y CP to QS2 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y CP to QPn 2.0 2.7 3.0 to 3.6 1.2 tPHL/tPLH Propagation delay g y STR to QPn 2.0 2.7 3.0 to 3.6 1.2 tPZH/tPZL 3-State Output enable time OE to Q n QP 2.0 2.7 3.0 to 3.6 1.2 tPHZ/tPLZ 3-State Output disable time OE to Q n QP 2.0 2.7 3.0 to 3.6 2.0 tw Clock pulse width HIGH or LOW 2.7 3.0 to 3.6 2.0 tw Strobe pulse width; HIGH 2.7 3.0 to 3.6 1.2 tsu Set-up time D to CP 2.0 2.7 3.0 to 3.6 1.2 tsu Set-u Set-up time CP to STR 2.0 2.7 3.0 to 3.6 43 31 25 22 16 13 34 25 20 34 25 20 MIN LIMITS -40 to +85 C TYP1 90 31 23 172 80 27 20 142 115 39 29 222 105 36 26 202 100 34 25 192 65 24 18 142 9 6 52 9 6 52 25 9 6 52 50 17 13 10
NO TAG
-40 to +125 C MAX MIN MAX
UNIT
58 43 34 51 38 30 75 55 44 68 50 40 65 48 38 40 32 26 41 30 24 41 30 24 26 19 15 51 38 30
70 51 41 61 45 36 90 66 53 82 60 48 77 56 45 49 37 30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1998 Jun 23
7
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
CONDITION SYMBOL PARAMETER WAVEFORM VCC (V) 1.2 Th Hold time D to CP 2.0 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V. 5 5 5 MIN
-40 to +85 C TYP1 -10 -4 -3 -2 NO TAG MAX
-40 to +125 C MIN MAX
UNIT
5 5 5 ns
1998 Jun 23
8
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
AC CHARACTERISTICS (Continued)
GND = 0 V; tr = tf 2.5ns; CL = 50pF SYMBOL PARAMETER CONDITION WAVEFORM VCC (V) 1.2 Th Hold time D to STR 2.0 2.7 3.0 to 3.6 2.0 fmax Maximum clock pulse frequency 2.7 3.0 to 3.6 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at VCC = 3.3 V. 5 5 5 14 19 24 MIN -40 to +85 C TYP1 -25 -9 -6 -52 52 70 872 5 5 5 12 16 20 MHz ns MAX -40 to +125 C MIN MAX UNIT
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V VM = 0.5 x VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3 V at VCC 2.7 V VX = VOL + 0.1 x VCC at VCC < 2.7 VY = VOH 0.3 V at VCC 2.7 V VY = VOH 0.1 x VCC at VCC < 2.7V
1/fmax VCC CP INPUT GND VM tW tPLH VM tPHL VCC CP INPUT GND tsu VCC STR INPUT GND VM tW tPLH VOH QS2 OUTPUT VOL tPLH VM VOL tPHL VOH QPn OUTPUT VM tPHL th VM
VOH QPn, QS1 OUTPUT VOL
SV01620
SV01619
Figure 1. Clock (CP) to output (QPn, QS1, QS2) propagation delays, the clock pulse width and the maximum clock frequency.
Figure 2. Strobe (STR) to output (QPn) propagation delays and the strobe pulse width and the clock set-up and hold times for strobe input.
1998 Jun 23
9
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
VCC OE INPUT GND tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled VY VM outputs disabled outputs enabled tPZL VM VX VM
VCC CP INPUT GND VM tsu th VCC D INPUT tPZH GND VOH QPn, QS1, QS2 OUTPUT VOL The shaded areas indicate when the input is permitted to change for predictable output performance. SV01617 VM VM tsu th
SV01618
Figure 3. 3-State enable and disable times for input OE.
Figure 4. Data set-up and hold times for the data input (D).
TEST CIRCUIT
90% VS1 Open GND VO D.U.T. RT CL= 50pF RL = 1k POSITIVE PULSE 10% RL = 1k NEGATIVE PULSE VM 10% tTHL (tf) tTLH (tr) 90% VM tW 90% VM 10% 0V 10% 0V Vl PULSE GENERATOR tTLH (tr) tTHL (tf) VI tW 90% VM VI
Vcc
S1
Test Circuit for Outputs
VM = 1.5V Input Pulse Definition
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open VS1 GND VCC < 2.7V 2.7-3.6V 4.5 V VI VCC 2.7V VCC VS1 2 < VCC 2 < VCC 2 < VCC
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SY00044
Figure 5. Load circuitry for switching times.
1998 Jun 23
10
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 Jun 23
11
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 Jun 23
12
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
NOTES
1998 Jun 23
13
Philips Semiconductors
Product specification
8-stage shift-and-store bus register
74LV4094
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98 9397-750-04662
Philips Semiconductors
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